The present invention relates generally to high speed, low-power SAR (successive approximation register) ADCs (analog-to-digital converters), and more particularly to an improved technique for operating an SAR ADC of generally conventional architecture to increase its conversion speed with little modification to its architecture or circuitry.
The basic conventional SAR ADC architecture is shown in FIG. 1, wherein a conventional CDAC (capacitive digital-to-analog converter) capacitor array 2 typically is connected to a charge summing conductor 7A which is connected to the one of the inputs of a comparator 3. The other input of comparator 3 is connected to a charge summing conductor 7B of a conventional xe2x80x9cdummyxe2x80x9d CDAC capacitor array 4. The output 4 of comparator 3 is connected to an input of a conventional SAR control logic circuit 5, which produces a plurality of digital output signals Dout on a digital bus 6 that is coupled to transistor switches in CDAC capacitor array 2. The transistor switches selectively couple the various capacitors in CDAC capacitor array 2 to a reference voltage conductor 9 conducting a reference voltage VREF+ or to a reference voltage conductor 16 conducting a reference voltage VREFxe2x88x92, which typically is ground.
FIG. 2 shows a typical external reference voltage amplifier 8 which produces VREF+ on conductor 9 within SAR ADC 1 of FIG. 1. There is a substantial bonding wire inductance 10A inside of an integrated circuit chip (indicated by the dashed line) on which the conventional SAR ADC 1 of FIG. 1 is formed. Inductance 10A is coupled between external conductor 9A and an internal conductor 9B conducting the internal value of VREF+which is applied by the transistor switches to the various capacitors of CDAC capacitor array 2 in accordance with digital signals Dout produced by SAR control logic 5 during the successive approximation testing/conversion operation. Reference numeral 13A in FIG. 2 represents series resistance of the transistor switch driving the CDAC, and conductor 9 and is shown as being lumped between node 9 and the output of an internal buffer 11.
Reference numeral 12 in FIG. 2 designates the widely variable capacitance CCDAC of the portion of CDAC capacitor array 2 which effectively xe2x80x9cloadsxe2x80x9d reference voltage amplifier 8 during the successive approximation process. If internal buffer 11 is omitted, then waveform V9A in FIG. 2 indicates xe2x80x9cringingxe2x80x9d of voltage that would be caused by bonding wire inductance 10A on conductor 9B when the CDAC array capacitance 12 varies suddenly due to switching that occurs in response to the digital signals 6 to establish the successive mid-range voltages needed for testing/conversion of each bit of the output word Dout.
Therefore, in the prior art it is usually necessary to provide above mentioned internal buffer circuit 11 to isolate the inductance 10A from the variable CDAC array capacitance 12 to avoid the kind of ringing indicated by waveform V9A. For high resolution ADCs, the CDAC capacitance has to be large, to achieve good noise and matching performance. Therefore, the switching load on the reference buffer is high for high resolution devices. Also, the speed at which the conversion is done puts a constraint on the settling time of the buffer. All these factors together increase the power consumption of the buffer 11. Undesirably, such an internal buffer 11 occupies a substantial amount of chip area and consumes a substantial amount of power.
One of the main drawbacks of high speed SAR ADCs that utilize internal CDACs (capacitive digital-to-analog converters) is that the external reference voltage amplifier driving the CDAC is subjected to the above mentioned widely changing capacitive load, depending on the value of the digital output word being generated to represent the analog input signal Vin. Consequently, if N is large, e.g., 16 bits or more, a large amount of time has to be allowed for the reference voltage amplifier 8 to settle to an accuracy corresponding to the N bit output word being produced.
FIG. 3 shows more details of CDAC capacitor array 2, wherein reference numeral 14 designates a plurality of binarily weighted CDAC array capacitors each having an upper terminal connected to charge summing conductor 7A and a lower terminal selectively coupled by a transistor switch circuit 15 to either VREF+ or VREFxe2x88x92 in response to the digital control signals 6 during the successive approximation bit testing/conversion procedure.
In the conventional SAR ADC 1 of FIG. 1, an analog input Vin=Vinxc2x1Vinxe2x88x92 is applied between an input conductor 17A of CDAC capacitor array 2 and an input conductor 17B of dummy CDAC capacitor array 4. Vin+ and Vinxe2x88x92 are sampled by means of input coupling capacitors in main CDAC array 2 and dummy CDAC array 4 during a sampling phase. At the end of the sampling phase, a conventional binary search algorithm is performed in response to the output of comparator 3 to establish a binary mid-range value for the output bit currently being tested/converted. Comparator 3 in effect compares the sampled analog input voltage to the present value of the binary mid-range value established in main CDAC array 2, and assigns a binary value of xe2x80x9c1xe2x80x9d to the bit presently being tested if the sampled analog input voltage exceeds the binary mid-range value, and otherwise assigns a binary xe2x80x9c0xe2x80x9d to the bit being tested/converted. As the conventional conversion process proceeds, it includes progressively testing and assigning xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d values to the output bits, one at a time, beginning with the MSB (most significant bit), to produce the output word Dout.
Each bit of the digital output word Dout, beginning with the MSB (most significant bit), is tested sequentially by comparator 3 to determine if that bit should be a xe2x80x9c1xe2x80x9d or a xe2x80x9c0xe2x80x9d. For an N bit accuracy of the ADC, the comparator should be able to resolve the difference of (Vref/2N) at its inputs. If N is increased, the comparator either (1) requires more time to settle, or (2) requires more bandwidth and consequently consumes more power if no more time is allowed for settling in order to resolve the more accurate bit testing decisions necessitated by the increasing of N.
In a typical SAR ADC, the analog to digital conversion proceeds one bit at a time until all of the bits of the digital output word are resolved, i.e., converted. All of the bits are processed at the full accuracy level required for an N-bit digital output word, so an equal amount of time is required to resolve each of the N bits of the output word Dout. Therefore, the amount of time required for a typical analog-to-digital conversion by an SAR ADC is:
Tcycle=Tsample+N*Tclock, 
where Tclock is the time required for resolving any one of the N bits of the output word.
The design of high-speed, high-resolution SAR ADCs is substantially limited by the speed of the comparator 3, by the bandwidth/power/settling time of the external reference voltage amplifier 8, and the internal settling time of the charge summing conductor 7A of the CDAC array 2. The higher the resolution of the SAR ADC, the more stringent the limitations on the amount of noise that can be present in the comparator, and the higher the amount of CDAC switching capacitance that the reference voltage amplifier must drive as it settles. The higher the desired speed of analog-to-digital conversion, the higher the speed, bandwidth and power consumption of comparator 3 must be, and the less time is available during which the voltage reference amplifier 8 must settle to the required accuracy level during the successive approximation testing/conversion of each bit. The amount of time required for the internal CDAC charge summing conductor 7A to settle to the required accuracy level includes two components, including (1) an RC time constant which determines the amount of time required for charge redistribution along the charge summing conductor 7A, and (2) the amount of time required for settling of the internal reference voltage node 9B connected to the transistor switches 15 (FIG. 3) associated with the various binarily weighted capacitors of the CDAC.
To summarize, the main bottlenecks for achieving high-speed, low-power operation of an SAR ADC are the settling time of the reference voltage amplifier 8, the CDAC charge redistribution time for the charge summing conductor 7A, and the delay of the comparator 3. The output of external reference voltage amplifier 8 is coupled through bonding wire inductance to a switched CDAC load, so every time the CDAC capacitor array is switched for the next bit decision, there is a current surge that must be supplied by a reference voltage amplifier output. This causes RLC xe2x80x9cringingxe2x80x9d of the reference voltage, which must be allowed to settle to an N-bit accuracy level, which for N equal to 16, is approximately 30 microvolts, and is approximately 0.5 millivolts at the 12 bit accuracy level. To avoid this ringing, the internal reference buffer 11 ordinarily is provided on the SAR ADC integrated circuit chip 1 to isolate the bonding wire inductance 10A and the CDAC capacitor array 12. Unfortunately, the internal reference buffer 11 requires a large amount of supply current in order to drive the large switched capacitive CDAC array loads 12 as the successive bits are tested/converted.
Apart from the settling of the reference voltage amplifier, the CDAC also requires additional time for charge redistribution before each successive bit of the output word can be tested. The charge redistribution time is an exponential settling time, and requires, for example, approximately 12 time constants to settle to the 16-bit accuracy level, 9 time constants to settle to the 12 bit accuracy level, and approximately 6.3 time constants to settle to the 8 bit accuracy level.
The comparator delay is the time required for the comparator to resolve the difference between the voltage applied between its inputs. This delay is inversely proportional to the minimum voltage difference that needs to be resolved, which in turn is proportional to the resolution of the ADC.
Referring to FIG. 4A, an example is shown of the voltage difference V7Axe2x88x92V7B applied between the inputs of comparator 3 wherein a large value designated xe2x80x9cOVERDRIVE Axe2x80x9d is applied and then a very small value designated xe2x80x9cOVERDRIVE Bxe2x80x9d is applied. FIG. 4B shows the internal structure of comparator 3, which includes a differential input stage 3A which drives the differential output stage 3B. Those skilled in the art will recognize that for the very low value of OVERDRIVE B, which in some cases might be only approximately Vref/65536 at the 16-bit accuracy level, the input stage 3A will drive output stage 3B much more slowly than if the much larger OVERDRIVE B is applied between the inputs of input stage 3A. Therefore, much more time must be allowed for comparator decisions at a high level of accuracy, e.g., at the 16-bit accuracy level, than is the case for comparator decisions at a lower accuracy level, e.g. at the 12 bit accuracy level. For example, for accuracy at the 16-bit level, the overdrive of the comparator input stage 3A for the xe2x80x9ccritical decisionxe2x80x9d is approximately 30 microvolts. At the 12 bit accuracy level, the comparator input stage overdrive for the critical decision is approximately 0.5 millivolts.
U.S. Pat. No. 4,620,179 (the ""179 patent) by Cooper et al., assigned to Harris Corp., discloses a successive approximation analog-to-digital conversion technique that attempts to solve the above shortcomings of the prior art by providing an N bit SAR ADC wherein the first X bits are approximated to within less than the desired accuracy for N bits successive approximation and the remaining N-X bits are approximated to within at least the desired accuracy for N bit successive approximation. The ""179 patent teaches that the error thereby introduced can be removed by performing an error correction operation. The ""179 patent also teaches that there should be only one error correction cycle because each additional error correction operation cycle would require a significant increase in conversion time and yet afford only nominal improvement in conversion accuracy. Column 6, line 13 et seq. describe the technique for determining how many of bits of the N bit converter should be converted at full scale accuracy after which the single error correction cycle should be performed.
However, since there are three possible results of the error correction operation of the ""179 patent, namely, incrementing the least significant bit, decrementing it, or performing no operation, it is not practical to perform the error correction operation in a single cycle. The ""179 patent fails to recognize that in most cases, multiple error correction operation should be performed, and also fails to recognize that every error correction operation need not be performed at the final accuracy of the analog-to-digital converter, and instead teaches that multiple error correction operations are not advisable. Finally, the single error correction cycle described in the ""179 patent requires too much time to perform and substantially reduces the advantage of the error correction process.
Thus, there is an unmet need for an improved way of operating an SAR ADC to provide substantially decreased analog-to-digital conversion time and reduced power consumption without substantially increasing complexity of the circuitry/architecture of the SAR ADC.
Accordingly, it is an object of the invention to provide an improved way of operating an SAR ADC so as to substantially decrease its analog-to-digital conversion time and/or substantially reduce its power consumption, without substantially increasing the complexity of the circuitry and without compromising on the accuracy of the SAR ADC.
It is another object of the invention to provide a technique for operating an SAR ADC which reduces the amount of time that must be allowed for a reference voltage amplifier to settle, which reduces the amount of time that must be allowed for internal CDAC charge redistribution, and which reduces the amount of time that must be allowed for comparator delay.
It is another object of the invention to provide a reduction of the analog-to-digital conversion time of an SAR ADC by at least a factor of 2 by changing its bit testing scheme, and without substantially changing the circuitry or architecture of the SAR.
It is another object of the invention to reduce the power dissipation of an SAR ADC primarily by changing its bit testing scheme, without reducing the analog-to-digital conversion time and without substantially changing the circuitry/architecture of the SAR ADC.
Briefly described, and in accordance with one embodiment, the present invention provides an SAR ADC which is operated by sampling an input voltage and redistributing a corresponding charge among a plurality of binarily weighted capacitors of a CDAC array to produce a representative voltage on a charge summing conductor. A successive approximation bit testing/conversion operation is performed at a first speed on a first group of bits, beginning with the MSB, to determine the bits of the first group with at least a first level of accuracy. A first error correction operation includes two cycles: performing a bit testing/conversion operation on a last bit of the first group and an incrementing or decrementing operation. Both are performed at a second speed which is lower than the first speed to determine the bits of the first group to at least a second level of accuracy which is more accurate than the first level of accuracy. Both the voltage on the charge summing conductor and the bits of the group are incremented or decremented as necessary to elevate the level of accuracy of the bits of the first group to at least the second level of accuracy. A similar successive approximation bit testing/conversion operation is performed at a lower second speed on a second group of bits to determine the bits of the second group with at least the second level of accuracy.